ClearCore Library
SysUtils.h
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1 /*
2  * Copyright (c) 2020 Teknic, Inc.
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22 
28 #ifndef __SYSUTILS_H__
29 #define __SYSUTILS_H__
30 
31 #include <stdint.h>
32 
33 // A EIC
34 // B REF
35 // ADC
36 // AC
37 // DAC
38 // PTC
39 // C SERCOM
40 // D SERCOM_ALT
41 // E TC
42 // F TCC
43 // G TCC/PDEC
44 // H USB
45 // I SDHC
46 // J I2S
47 // K PCC
48 // L GMAC
49 // M GCLK/AC
50 // N CCL
51 
53 typedef enum {
54  /* The pin is controlled by the assoc. signal of peripheral... */
55  PER_EXTINT = 0, /* A. */
56  PER_ANALOG, /* B. */
57  PER_SERCOM, /* C. */
58  PER_SERCOM_ALT, /* D. */
59  PER_TIMER, /* E. */
60  PER_TIMER_ALT, /* F. */
61  PER_TIMER_PDEC, /* G. */
62  PER_USB, /* H. */
63  PER_SDHC, /* I. */
64  PER_I2S, /* J. */
65  PER_PCC, /* K. */
66  PER_GMAC, /* L. */
67  PER_GCLK_AC, /* M. */
68  PER_CCL, /* N. */
69 } PerType;
70 
75 #define PMUX_SELECTION(GPIO_PORT, GPIO_PIN, PER_TYPE) \
76 if ((GPIO_PIN) & 1) { \
77  PORT->Group[(GPIO_PORT)].PMUX[(GPIO_PIN) >> 1].bit.PMUXO = (PER_TYPE); \
78 } \
79 else { \
80  PORT->Group[(GPIO_PORT)].PMUX[(GPIO_PIN) >> 1].bit.PMUXE = (PER_TYPE); \
81 }
82 
86 #define DATA_OUTPUT_STATE(GPIO_PORT, DATA_MASK, STATE) \
87 if ((STATE)) { \
88  PORT->Group[(GPIO_PORT)].OUTSET.reg = (DATA_MASK); \
89 } \
90 else { \
91  PORT->Group[(GPIO_PORT)].OUTCLR.reg = (DATA_MASK); \
92 }
93 
97 #define PMUX_ENABLE(GPIO_PORT, GPIO_PIN) \
98 PORT->Group[(GPIO_PORT)].PINCFG[(GPIO_PIN)].bit.PMUXEN = 1
99 
103 #define PMUX_DISABLE(GPIO_PORT, GPIO_PIN) \
104 PORT->Group[(GPIO_PORT)].PINCFG[(GPIO_PIN)].bit.PMUXEN = 0
105 
109 #define PIN_CONFIGURATION(GPIO_PORT, GPIO_PIN, CONFIG) \
110 PORT->Group[(GPIO_PORT)].PINCFG[(GPIO_PIN)].reg = (CONFIG)
111 
115 #define DATA_DIRECTION_OUTPUT(GPIO_PORT, DATA_MASK) \
116 PORT->Group[(GPIO_PORT)].DIRSET.reg = (DATA_MASK)
117 
121 #define DATA_DIRECTION_INPUT(GPIO_PORT, DATA_MASK) \
122 PORT->Group[(GPIO_PORT)].DIRCLR.reg = (DATA_MASK)
123 
127 #define SYNCBUSY_WAIT(PER, BITMASK) \
128 while ((PER)->SYNCBUSY.reg & (BITMASK)) { \
129  continue; \
130 }
131 
135 #define CLOCK_ENABLE(BUS, BIT) \
136 MCLK->BUS.bit.BIT = 1
137 
166 #define SET_CLOCK_SOURCE(PER_GCLK_ID, GCLK_INDEX) \
167 GCLK->PCHCTRL[(PER_GCLK_ID)].bit.CHEN = 0; \
168 while (GCLK->PCHCTRL[(PER_GCLK_ID)].bit.CHEN) { \
169  continue; \
170 } \
171 GCLK->PCHCTRL[(PER_GCLK_ID)].bit.GEN = GCLK_PCHCTRL_GEN((GCLK_INDEX)); \
172 GCLK->PCHCTRL[(PER_GCLK_ID)].bit.CHEN = 1; \
173 while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL((GCLK_INDEX))) { \
174  continue; \
175 }
176 
179 #ifndef max
180 #define max(a, b) (((a) > (b)) ? (a) : (b))
181 #endif
182 
186 #ifndef min
187 #define min(a, b) (((a) < (b)) ? (a) : (b))
188 #endif
189 
190 #ifdef __cplusplus
191 extern "C" {
192 #endif
193 
202 void GClkFreqUpdate(uint8_t gclkIndex, uint32_t freqReq);
203 
204 #ifdef __cplusplus
205 }
206 #endif
207 #endif // __SYSUTILS_H__
PerType
Definition: SysUtils.h:53
void GClkFreqUpdate(uint8_t gclkIndex, uint32_t freqReq)
Update GCLK frequency.