28 #ifndef __HARDWAREMAPPING_H__ 29 #define __HARDWAREMAPPING_H__ 47 #pragma GCC diagnostic push 48 #pragma GCC diagnostic ignored "-Wpedantic" 49 #pragma GCC diagnostic ignored "-Wmissing-field-initializers" 51 #ifndef HIDE_FROM_DOXYGEN 52 const PeripheralRoute _5VOB_MON = {
69 const PeripheralRoute Com0_CTS_MISO = {
86 const PeripheralRoute Com0_RTS_SS = {
103 const PeripheralRoute Com0_RX_SCK = {
108 .extIntAvail =
false,
120 const PeripheralRoute Com0_TX_MOSI = {
125 .extIntAvail =
false,
137 const PeripheralRoute Com1_CTS_MISO = {
142 .extIntAvail =
false,
154 const PeripheralRoute Com1_RTS_SS = {
159 .extIntAvail =
false,
171 const PeripheralRoute Com1_RX_SCK = {
176 .extIntAvail =
false,
188 const PeripheralRoute Com1_TX_MOSI = {
193 .extIntAvail =
false,
205 const PeripheralRoute Aout00 = {
210 .extIntAvail =
false,
222 const PeripheralRoute IN00n_Aout00n = {
227 .extIntAvail =
false,
239 const PeripheralRoute IN01n = {
244 .extIntAvail =
false,
256 const PeripheralRoute IN02n = {
261 .extIntAvail =
false,
273 const PeripheralRoute IN03n = {
278 .extIntAvail =
false,
290 const PeripheralRoute IN04n = {
295 .extIntAvail =
false,
307 const PeripheralRoute IN05n = {
312 .extIntAvail =
false,
324 const PeripheralRoute IN06n_QuadA = {
341 const PeripheralRoute IN07n_QuadB = {
358 const PeripheralRoute IN08n_QuadI = {
375 const PeripheralRoute IN09n_AIN09 = {
392 const PeripheralRoute IN10n_AIN10 = {
409 const PeripheralRoute IN11n_AIN11 = {
426 const PeripheralRoute IN12n_AIN12 = {
443 const PeripheralRoute MicroSD_MISO = {
448 .extIntAvail =
false,
460 const PeripheralRoute MicroSD_MOSI = {
465 .extIntAvail =
false,
477 const PeripheralRoute MicroSD_SCK = {
482 .extIntAvail =
false,
494 const PeripheralRoute MicroSD_SS = {
499 .extIntAvail =
false,
511 const PeripheralRoute Mtr_CLK_01 = {
516 .extIntAvail =
false,
528 const PeripheralRoute Mtr_CLK_23 = {
533 .extIntAvail =
false,
545 const PeripheralRoute Mtr0_An_SCTx = {
550 .extIntAvail =
false,
562 const PeripheralRoute Mtr0_B = {
567 .extIntAvail =
false,
579 const PeripheralRoute Mtr0_HLFB_SCRx = {
596 const PeripheralRoute Mtr1_An = {
601 .extIntAvail =
false,
613 const PeripheralRoute Mtr1_B = {
618 .extIntAvail =
false,
630 const PeripheralRoute Mtr1_HLFB = {
647 const PeripheralRoute Mtr2_An_Sdrvr2_PWMA = {
652 .extIntAvail =
false,
664 const PeripheralRoute Mtr2_B_Sdrvr2_PWMB = {
669 .extIntAvail =
false,
681 const PeripheralRoute Mtr2_HLFB_Sdrvr2_Trig = {
698 const PeripheralRoute Mtr3_An_Sdrvr3_PWMA = {
703 .extIntAvail =
false,
715 const PeripheralRoute Mtr3_B_Sdrvr3_PWMB = {
720 .extIntAvail =
false,
732 const PeripheralRoute Mtr3_HLFB_Sdrvr3_Trig = {
749 const PeripheralRoute OUT00 = {
754 .extIntAvail =
false,
766 const PeripheralRoute OUT01 = {
771 .extIntAvail =
false,
783 const PeripheralRoute OUT02 = {
788 .extIntAvail =
false,
800 const PeripheralRoute OUT03 = {
805 .extIntAvail =
false,
817 const PeripheralRoute OUT04_ENABLE04 = {
822 .extIntAvail =
false,
834 const PeripheralRoute OUT05_ENABLE05 = {
839 .extIntAvail =
false,
851 const PeripheralRoute OutFault_04or05 = {
856 .extIntAvail =
false,
868 const PeripheralRoute PHY_INT = {
885 const PeripheralRoute PHY_MDC = {
890 .extIntAvail =
false,
902 const PeripheralRoute PHY_MDIO = {
907 .extIntAvail =
false,
919 const PeripheralRoute PHY_RXD0 = {
924 .extIntAvail =
false,
936 const PeripheralRoute PHY_RXD1 = {
941 .extIntAvail =
false,
953 const PeripheralRoute PHY_RXDV = {
958 .extIntAvail =
false,
970 const PeripheralRoute PHY_RXER = {
975 .extIntAvail =
false,
987 const PeripheralRoute PHY_TXCLK = {
992 .extIntAvail =
false,
1004 const PeripheralRoute PHY_TXD0 = {
1009 .extIntAvail =
false,
1021 const PeripheralRoute PHY_TXD1 = {
1026 .extIntAvail =
false,
1038 const PeripheralRoute PHY_TXEN = {
1043 .extIntAvail =
false,
1055 const PeripheralRoute Polarity04_PWM04A = {
1060 .extIntAvail =
false,
1072 const PeripheralRoute Polarity04S_PWM04B = {
1077 .extIntAvail =
false,
1089 const PeripheralRoute Polarity05_PWM05A = {
1094 .extIntAvail =
false,
1106 const PeripheralRoute Polarity05S_PWM05B = {
1111 .extIntAvail =
false,
1123 const PeripheralRoute RESETn = {
1125 .gpioPort = NOT_A_PORT,
1128 .extIntAvail =
false,
1133 .sercomPadNum = 255,
1140 const PeripheralRoute Sdrvr2_iMon = {
1145 .extIntAvail =
false,
1150 .sercomPadNum = 255,
1157 const PeripheralRoute Sdrvr3_iMon = {
1162 .extIntAvail =
false,
1167 .sercomPadNum = 255,
1174 const PeripheralRoute SR_CLK = {
1179 .extIntAvail =
false,
1191 const PeripheralRoute SR_DATA = {
1196 .extIntAvail =
false,
1208 const PeripheralRoute SR_DATA_RET = {
1213 .extIntAvail =
false,
1225 const PeripheralRoute SR_ENn = {
1230 .extIntAvail =
false,
1235 .sercomPadNum = 255,
1242 const PeripheralRoute SR_LOAD = {
1247 .extIntAvail =
false,
1252 .sercomPadNum = 255,
1259 const PeripheralRoute SWCLK = {
1264 .extIntAvail =
false,
1276 const PeripheralRoute SWDIO = {
1281 .extIntAvail =
false,
1293 const PeripheralRoute SWO = {
1298 .extIntAvail =
false,
1310 const PeripheralRoute SYS_CLK = {
1315 .extIntAvail =
false,
1327 const PeripheralRoute USB_DM = {
1332 .extIntAvail =
false,
1344 const PeripheralRoute USB_DP = {
1349 .extIntAvail =
false,
1361 const PeripheralRoute Vsupply_MON_IO_4and5_RST = {
1366 .extIntAvail =
false,
1371 .sercomPadNum = 255,
1378 const PeripheralRoute XBee_CTS_IN = {
1383 .extIntAvail =
false,
1395 const PeripheralRoute XBee_RTS_OUT = {
1400 .extIntAvail =
false,
1412 const PeripheralRoute XBee_Rx_IN = {
1417 .extIntAvail =
false,
1429 const PeripheralRoute XBee_Tx_OUT = {
1434 .extIntAvail =
false,
1446 #endif // HIDE_FROM_DOXYGEN 1449 #pragma GCC diagnostic pop 1458 #endif // __HARDWAREMAPPING_H__ Defines the Peripheral Route structure, used in HardwareMapping.
Namespace to encompass the ClearCore board API.
Definition: AdcManager.h:36
Base class for all connector classes.