28#ifndef __HARDWAREMAPPING_H__
29#define __HARDWAREMAPPING_H__
47#pragma GCC diagnostic push
48#pragma GCC diagnostic ignored "-Wpedantic"
49#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
51#ifndef HIDE_FROM_DOXYGEN
52const PeripheralRoute _5VOB_MON = {
69const PeripheralRoute Com0_CTS_MISO = {
86const PeripheralRoute Com0_RTS_SS = {
103const PeripheralRoute Com0_RX_SCK = {
108 .extIntAvail =
false,
120const PeripheralRoute Com0_TX_MOSI = {
125 .extIntAvail =
false,
137const PeripheralRoute Com1_CTS_MISO = {
142 .extIntAvail =
false,
154const PeripheralRoute Com1_RTS_SS = {
159 .extIntAvail =
false,
171const PeripheralRoute Com1_RX_SCK = {
176 .extIntAvail =
false,
188const PeripheralRoute Com1_TX_MOSI = {
193 .extIntAvail =
false,
205const PeripheralRoute Aout00 = {
210 .extIntAvail =
false,
222const PeripheralRoute IN00n_Aout00n = {
227 .extIntAvail =
false,
239const PeripheralRoute IN01n = {
244 .extIntAvail =
false,
256const PeripheralRoute IN02n = {
261 .extIntAvail =
false,
273const PeripheralRoute IN03n = {
278 .extIntAvail =
false,
290const PeripheralRoute IN04n = {
295 .extIntAvail =
false,
307const PeripheralRoute IN05n = {
312 .extIntAvail =
false,
324const PeripheralRoute IN06n_QuadA = {
341const PeripheralRoute IN07n_QuadB = {
358const PeripheralRoute IN08n_QuadI = {
375const PeripheralRoute IN09n_AIN09 = {
392const PeripheralRoute IN10n_AIN10 = {
409const PeripheralRoute IN11n_AIN11 = {
426const PeripheralRoute IN12n_AIN12 = {
443const PeripheralRoute MicroSD_MISO = {
448 .extIntAvail =
false,
460const PeripheralRoute MicroSD_MOSI = {
465 .extIntAvail =
false,
477const PeripheralRoute MicroSD_SCK = {
482 .extIntAvail =
false,
494const PeripheralRoute MicroSD_SS = {
499 .extIntAvail =
false,
511const PeripheralRoute Mtr_CLK_01 = {
516 .extIntAvail =
false,
528const PeripheralRoute Mtr_CLK_23 = {
533 .extIntAvail =
false,
545const PeripheralRoute Mtr0_An_SCTx = {
550 .extIntAvail =
false,
562const PeripheralRoute Mtr0_B = {
567 .extIntAvail =
false,
579const PeripheralRoute Mtr0_HLFB_SCRx = {
596const PeripheralRoute Mtr1_An = {
601 .extIntAvail =
false,
613const PeripheralRoute Mtr1_B = {
618 .extIntAvail =
false,
630const PeripheralRoute Mtr1_HLFB = {
647const PeripheralRoute Mtr2_An_Sdrvr2_PWMA = {
652 .extIntAvail =
false,
664const PeripheralRoute Mtr2_B_Sdrvr2_PWMB = {
669 .extIntAvail =
false,
681const PeripheralRoute Mtr2_HLFB_Sdrvr2_Trig = {
698const PeripheralRoute Mtr3_An_Sdrvr3_PWMA = {
703 .extIntAvail =
false,
715const PeripheralRoute Mtr3_B_Sdrvr3_PWMB = {
720 .extIntAvail =
false,
732const PeripheralRoute Mtr3_HLFB_Sdrvr3_Trig = {
749const PeripheralRoute OUT00 = {
754 .extIntAvail =
false,
766const PeripheralRoute OUT01 = {
771 .extIntAvail =
false,
783const PeripheralRoute OUT02 = {
788 .extIntAvail =
false,
800const PeripheralRoute OUT03 = {
805 .extIntAvail =
false,
817const PeripheralRoute OUT04_ENABLE04 = {
822 .extIntAvail =
false,
834const PeripheralRoute OUT05_ENABLE05 = {
839 .extIntAvail =
false,
851const PeripheralRoute OutFault_04or05 = {
856 .extIntAvail =
false,
868const PeripheralRoute PHY_INT = {
885const PeripheralRoute PHY_MDC = {
890 .extIntAvail =
false,
902const PeripheralRoute PHY_MDIO = {
907 .extIntAvail =
false,
919const PeripheralRoute PHY_RXD0 = {
924 .extIntAvail =
false,
936const PeripheralRoute PHY_RXD1 = {
941 .extIntAvail =
false,
953const PeripheralRoute PHY_RXDV = {
958 .extIntAvail =
false,
970const PeripheralRoute PHY_RXER = {
975 .extIntAvail =
false,
987const PeripheralRoute PHY_TXCLK = {
992 .extIntAvail =
false,
1004const PeripheralRoute PHY_TXD0 = {
1009 .extIntAvail =
false,
1021const PeripheralRoute PHY_TXD1 = {
1026 .extIntAvail =
false,
1038const PeripheralRoute PHY_TXEN = {
1043 .extIntAvail =
false,
1055const PeripheralRoute Polarity04_PWM04A = {
1060 .extIntAvail =
false,
1072const PeripheralRoute Polarity04S_PWM04B = {
1077 .extIntAvail =
false,
1089const PeripheralRoute Polarity05_PWM05A = {
1094 .extIntAvail =
false,
1106const PeripheralRoute Polarity05S_PWM05B = {
1111 .extIntAvail =
false,
1123const PeripheralRoute RESETn = {
1125 .gpioPort = NOT_A_PORT,
1128 .extIntAvail =
false,
1133 .sercomPadNum = 255,
1140const PeripheralRoute Sdrvr2_iMon = {
1145 .extIntAvail =
false,
1150 .sercomPadNum = 255,
1157const PeripheralRoute Sdrvr3_iMon = {
1162 .extIntAvail =
false,
1167 .sercomPadNum = 255,
1174const PeripheralRoute SR_CLK = {
1179 .extIntAvail =
false,
1191const PeripheralRoute SR_DATA = {
1196 .extIntAvail =
false,
1208const PeripheralRoute SR_DATA_RET = {
1213 .extIntAvail =
false,
1225const PeripheralRoute SR_ENn = {
1230 .extIntAvail =
false,
1235 .sercomPadNum = 255,
1242const PeripheralRoute SR_LOAD = {
1247 .extIntAvail =
false,
1252 .sercomPadNum = 255,
1259const PeripheralRoute SWCLK = {
1264 .extIntAvail =
false,
1276const PeripheralRoute SWDIO = {
1281 .extIntAvail =
false,
1293const PeripheralRoute SWO = {
1298 .extIntAvail =
false,
1310const PeripheralRoute SYS_CLK = {
1315 .extIntAvail =
false,
1327const PeripheralRoute USB_DM = {
1332 .extIntAvail =
false,
1344const PeripheralRoute USB_DP = {
1349 .extIntAvail =
false,
1361const PeripheralRoute Vsupply_MON_IO_4and5_RST = {
1366 .extIntAvail =
false,
1371 .sercomPadNum = 255,
1378const PeripheralRoute XBee_CTS_IN = {
1383 .extIntAvail =
false,
1395const PeripheralRoute XBee_RTS_OUT = {
1400 .extIntAvail =
false,
1412const PeripheralRoute XBee_Rx_IN = {
1417 .extIntAvail =
false,
1429const PeripheralRoute XBee_Tx_OUT = {
1434 .extIntAvail =
false,
1449#pragma GCC diagnostic pop
Base class for all connector classes.
Defines the Peripheral Route structure, used in HardwareMapping.
Namespace to encompass the ClearCore board API.
Definition AdcManager.h:36