32 #ifndef __SERIALBASE_H__ 33 #define __SERIALBASE_H__ 44 #ifndef SERIAL_BUFFER_SIZE 45 #define SERIAL_BUFFER_SIZE 64 49 #ifndef SERCOM_NVIC_RX_PRIORITY 50 #define SERCOM_NVIC_RX_PRIORITY (static_cast<IRQn_Type>(1)) 53 #ifndef SERCOM_NVIC_TX_PRIORITY 54 #define SERCOM_NVIC_TX_PRIORITY (static_cast<IRQn_Type>(1)) 57 #ifndef SERCOM_NVIC_ERR_PRIORITY 58 #define SERCOM_NVIC_ERR_PRIORITY (static_cast<IRQn_Type>(7)) 79 static const int16_t
EOB = -1;
128 operator bool()
const {
206 void Flush()
override;
226 virtual bool Speed(uint32_t bitsPerSecond)
override;
248 bool SendChar(uint8_t charToSend)
override;
296 return m_flowControl;
313 bool RtsMode(CtrlLineModes mode);
377 bool StopBits(uint8_t bits)
override;
390 bool CharSize(uint8_t size)
override;
392 #ifndef HIDE_FROM_DOXYGEN 396 operator bool()
override {
411 void SpiClock(SpiClockPolarities polarity, SpiClockPhases phase);
448 uint8_t
const *writeBuf, uint8_t *readBuf, int32_t len);
466 uint8_t
const *writeBuf, uint8_t *readBuf, int32_t len);
531 #ifndef HIDE_FROM_DOXYGEN 555 void IrqHandlerException();
563 PortModes m_portMode;
564 SpiClockPolarities m_polarity;
565 SpiClockPhases m_phase;
566 CtrlLineModes m_ssMode;
567 CtrlLineModes m_rtsMode;
574 const PeripheralRoute *m_ctsMisoInfo;
575 const PeripheralRoute *m_rtsSsInfo;
576 const PeripheralRoute *m_rxSckInfo;
577 const PeripheralRoute *m_txMosiInfo;
580 uint8_t m_peripheral;
588 DmaChannels m_dmaRxChannel;
589 DmaChannels m_dmaTxChannel;
594 SerialBase(
const PeripheralRoute *ctsMisoInfo,
595 const PeripheralRoute *rtsSsInfo,
596 const PeripheralRoute *rxSckInfo,
597 const PeripheralRoute *txMosiInfo,
609 void WaitOneCharTime();
615 void EnableDreInterruptUart();
619 void DisableDreInterruptUart();
623 void EnableRxcInterruptUart();
627 void DisableRxcInterruptUart();
635 volatile uint32_t m_inHead, m_inTail;
636 volatile uint32_t m_outHead, m_outTail;
645 void PortEnable(
bool initializing =
false);
651 uint32_t NextIndex(uint32_t currentIndex) {
669 bool RtsSsPinState(CtrlLineModes mode);
673 #endif // __SERIALBASE_H__ bool SpiSsMode(CtrlLineModes mode)
Change the SPI Slave Select mode.
Base class for interacting with all ClearCore serial.
Definition: ISerial.h:50
A standardized ClearCore Serial interface.
enum ClearCore::ISerial::_Parities Parities
ClearCore ARM Serial Port base class.
Definition: SerialBase.h:66
uint32_t reg
Definition: SerialBase.h:90
bool StopBits(uint8_t bits) override
bool RtsMode(CtrlLineModes mode)
Change the serial RTS mode.
int32_t AvailableForRead() override
Defines the Peripheral Route structure, used in HardwareMapping.
uint8_t SpiTransferData(uint8_t data)
SerialErrorStatusRegister()
Definition: SerialBase.h:113
uint32_t SerialOverflowError
Definition: SerialBase.h:107
bool FlowControl()
Return whether UART CTS/RTS flow control is enabled.
Definition: SerialBase.h:295
void SerialBreak(bool enable)
Initiate a Serial Break.
Serial Peripheral Interface (SPI) mode.
Definition: SerialBase.h:150
SerialErrorStatusRegister ErrorStatusAccum(SerialErrorStatusRegister mask=UINT32_MAX)
Accumulating clear on read accessor for any error status bits that were asserted sometime since the p...
Leading edge samples, trailing edge changes.
Definition: SerialBase.h:168
SpiClockPolarities
Definition: SerialBase.h:156
SpiClockPhases
Definition: SerialBase.h:166
struct ClearCore::SerialBase::SerialErrorStatusRegister::@4 bit
Leading edge changes, trailing edge samples.
Definition: SerialBase.h:170
Universal Asynchronous Receiver-Transmitter (UART) mode.
Definition: SerialBase.h:148
SCK is low when idle.
Definition: SerialBase.h:158
PortModes
Definition: SerialBase.h:146
DataOrders
Definition: SerialBase.h:136
SerialErrorStatusRegister(uint32_t val)
Definition: SerialBase.h:120
virtual void PortClose() override
bool SpiTransferDataAsync(uint8_t const *writeBuf, uint8_t *readBuf, int32_t len)
SPI's asynchronous multi-byte transmit and receive function.
#define SERIAL_BUFFER_SIZE
Definition: SerialBase.h:45
Parities Parity() override
Return current port UART transmission format.
Definition: SerialBase.h:365
int16_t CharPeek() override
Attempt to get the next character from the serial channel without pulling the character out of the bu...
bool CharSize(uint8_t size) override
Change the number of bits in a character.
CtrlLineModes
Definition: SerialBase.h:176
virtual void PortOpen() override
Namespace to encompass the ClearCore board API.
Definition: AdcManager.h:36
void SpiClock(SpiClockPolarities polarity, SpiClockPhases phase)
Change the polarity and phase for the SPI clock.
void WaitForTransmitIdle() override
bool PortIsOpen() override
Return whether or not the port is open.
SCK is high when idle.
Definition: SerialBase.h:160
Control line is controlled by hardware.
Definition: SerialBase.h:182
uint32_t SerialFrameError
Definition: SerialBase.h:99
void DataOrder(DataOrders newOrder)
Change the data order for the port.
static const int16_t BREAK_DETECTED
Definition: SerialBase.h:74
void FlushInput() override
uint32_t SerialParityError
Definition: SerialBase.h:103
bool SpiAsyncWaitComplete()
Block until asynchronous transfers are completed.
virtual uint32_t Speed() override
Gets the baud rate of the port.
Definition: SerialBase.h:231
Control line is in the OFF state.
Definition: SerialBase.h:178
Most significant bit first.
Definition: SerialBase.h:138
int16_t CharGet() override
Attempt to read the next character from serial channel.
Least significant bit first.
Definition: SerialBase.h:140
Definition: SerialBase.h:86
Control line is in the ON state.
Definition: SerialBase.h:180
bool CtsState()
Read the serial CTS state.
bool SendChar(uint8_t charToSend) override
Send an ascii character on the serial channel.
bool PortMode(PortModes newMode)
Setup the port mode.
static const int16_t EOB
Definition: SerialBase.h:79
int32_t AvailableForWrite() override
Determines the number of characters available in the transmit buffer.
DMA Peripheral Manager for the ClearCore Board.