ClearCore Library
Phy.h
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1 /*
2 * Copyright (c) 2020 Teknic, Inc.
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4 * Permission is hereby granted, free of charge, to any person obtaining a copy
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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22 
27 /************************ PHY ****************************/
28 #ifndef __PHY_H__
29 #define __PHY_H__
30 
31 #ifndef HIDE_FROM_DOXYGEN
32 // Ethernet PHY Operations
33 #define PHY_READ_OP 2
34 #define PHY_WRITE_OP 1
35 
36 // Ethernet PHY Auto-Negotiated Modes
37 #define PHY_CTRL_AN_MSK 0x0007
38 #define BASE_10_HDX 0x1
39 #define BASE_10_FDX 0x5
40 #define BASE_100_HDX 0x2
41 #define BASE_100_FDX 0x6
42 
43 #define PHY_CTRL_AN_SPD_MSK 0x2
44 #define PHY_CTRL_AN_FD_MSK 0x4
45 
46 // Ethernet PHY Registers
47 #define PHY_B_CTRL 0x00
48 #define PHY_B_STATUS 0x01
49 #define PHY_ID_1 0x02
50 #define PHY_ID_2 0x03
51 #define PHY_ANA 0x04
52 #define PHY_ANLP 0x05
53 #define PHY_ANE 0x06
54 #define PHY_ANNP 0x07
55 #define PHY_LPNP 0x08
56 // reserved
57 #define PHY_DRC 0x10
58 #define PHY_AFE_CTRL 0x11
59 // reserved
60 #define PHY_RXER_COUNT 0x15
61 #define PHY_ICS 0x1B
62 #define PHY_LMD 0x1D
63 #define PHY_CTRL_1 0x1E
64 #define PHY_CTRL_2 0x1F
65 
66 // PHY_B_CTRL: Ethernet PHY Register 0h - Basic Control
67 #define PHY_B_CTRL_COLEN_Pos 7
68 #define PHY_B_CTRL_COLEN (_U_(0x1) << PHY_B_CTRL_COLEN_Pos)
69 #define PHY_B_CTRL_DPLX_Pos 8
70 #define PHY_B_CTRL_DPLX (_U_(0x1) << PHY_B_CTRL_DPLX_Pos)
71 #define PHY_B_CTRL_RAN_Pos 9
72 #define PHY_B_CTRL_RAN (_U_(0x1) << PHY_B_CTRL_RAN_Pos)
73 #define PHY_B_CTRL_ISO_Pos 10
74 #define PHY_B_CTRL_ISO (_U_(0x1) << PHY_B_CTRL_ISO_Pos)
75 #define PHY_B_CTRL_PD_Pos 11
76 #define PHY_B_CTRL_PD (_U_(0x1) << PHY_B_CTRL_PD_Pos)
77 #define PHY_B_CTRL_ANEN_Pos 12
78 #define PHY_B_CTRL_ANEN (_U_(0x1) << PHY_B_CTRL_ANEN_Pos)
79 #define PHY_B_CTRL_SPD_Pos 13
80 #define PHY_B_CTRL_SPD (_U_(0x1) << PHY_B_CTRL_SPD_Pos)
81 #define PHY_B_CTRL_LB_Pos 14
82 #define PHY_B_CTRL_LB (_U_(0x1) << PHY_B_CTRL_LB_Pos)
83 #define PHY_B_CTRL_RES_Pos 15
84 #define PHY_B_CTRL_RES (_U_(0x1) << PHY_B_CTRL_RES_Pos)
85 
86 // PHY_B_STATUS: Ethernet PHY Register 1h - Basic Status
87 #define PHY_B_STATUS_EC_Pos 0
88 #define PHY_B_STATUS_EC (_U_(0x1) << PHY_B_STATUS_EC_Pos)
89 #define PHY_B_STATUS_JAB_Pos 1
90 #define PHY_B_STATUS_JAB (_U_(0x1) << PHY_B_STATUS_JAB_Pos)
91 #define PHY_B_STATUS_LU_Pos 2
92 #define PHY_B_STATUS_LU (_U_(0x1) << PHY_B_STATUS_LU_Pos)
93 #define PHY_B_STATUS_AN_Pos 3
94 #define PHY_B_STATUS_AN (_U_(0x1) << PHY_B_STATUS_AN_Pos)
95 #define PHY_B_STATUS_REMF_Pos 4
96 #define PHY_B_STATUS_REMF (_U_(0x1) << PHY_B_STATUS_REMF_Pos)
97 #define PHY_B_STATUS_ANC_Pos 5
98 #define PHY_B_STATUS_ANC (_U_(0x1) << PHY_B_STATUS_ANC_Pos)
99 #define PHY_B_STATUS_NPRE_Pos 6
100 #define PHY_B_STATUS_NPRE (_U_(0x1) << PHY_B_STATUS_NPRE_Pos)
101 #define PHY_B_STATUS_TBTHD_Pos 11
102 #define PHY_B_STATUS_TBTHD (_U_(0x1) << PHY_B_STATUS_TBTHD_Pos)
103 #define PHY_B_STATUS_TBTFD_Pos 12
104 #define PHY_B_STATUS_TBTFD (_U_(0x1) << PHY_B_STATUS_TBTFD_Pos)
105 #define PHY_B_STATUS_HBTHD_Pos 13
106 #define PHY_B_STATUS_HBTHD (_U_(0x1) << PHY_B_STATUS_HBTHD_Pos)
107 #define PHY_B_STATUS_HBTFD_Pos 14
108 #define PHY_B_STATUS_HBTFD (_U_(0x1) << PHY_B_STATUS_HBTFD_Pos)
109 #define PHY_B_STATUS_TFOUR_Pos 15
110 #define PHY_B_STATUS_TFOUR (_U_(0x1) << PHY_B_STATUS_TFOUR_Pos)
111 
112 // PHY_ICS : Ethernet PHY Register 1Bh - Interrupt Control/Status
113 #define PHY_ICS_LU_Pos 0
114 #define PHY_ICS_LU (_U_(0x1) << PHY_ICS_LU_Pos)
115 #define PHY_ICS_RF_Pos 1
116 #define PHY_ICS_RF (_U_(0x1) << PHY_ICS_RF_Pos)
117 #define PHY_ICS_LD_Pos 2
118 #define PHY_ICS_LD (_U_(0x1) << PHY_ICS_LD_Pos)
119 #define PHY_ICS_LPA_Pos 3
120 #define PHY_ICS_LPA (_U_(0x1) << PHY_ICS_LPAEN_Pos)
121 #define PHY_ICS_PDF_Pos 4
122 #define PHY_ICS_PDF (_U_(0x1) << PHY_ICS_PDF_Pos)
123 #define PHY_ICS_PRX_Pos 5
124 #define PHY_ICS_PRX (_U_(0x1) << PHY_ICS_PRX_Pos)
125 #define PHY_ICS_RXER_Pos 6
126 #define PHY_ICS_RXER (_U_(0x1) << PHY_ICS_RXER_Pos)
127 #define PHY_ICS_JAB_Pos 7
128 #define PHY_ICS_JAB (_U_(0x1) << PHY_ICS_JAB_Pos)
129 #define PHY_ICS_LUEN_Pos 8
130 #define PHY_ICS_LUEN (_U_(0x1) << PHY_ICS_LUEN_Pos)
131 #define PHY_ICS_RFEN_Pos 9
132 #define PHY_ICS_RFEN (_U_(0x1) << PHY_ICS_RFEN_Pos)
133 #define PHY_ICS_LDEN_Pos 10
134 #define PHY_ICS_LDEN (_U_(0x1) << PHY_ICS_LDEN_Pos)
135 #define PHY_ICS_LPAEN_Pos 11
136 #define PHY_ICS_LPAEN (_U_(0x1) << PHY_ICS_LPAEN_Pos)
137 #define PHY_ICS_PDFEN_Pos 12
138 #define PHY_ICS_PDFEN (_U_(0x1) << PHY_ICS_PDFEN_Pos)
139 #define PHY_ICS_PRXEN_Pos 13
140 #define PHY_ICS_PRXEN (_U_(0x1) << PHY_ICS_PRXEN_Pos)
141 #define PHY_ICS_RXEREN_Pos 14
142 #define PHY_ICS_RXEREN (_U_(0x1) << PHY_ICS_RXEREN_Pos)
143 #define PHY_ICS_JABEN_Pos 15
144 #define PHY_ICS_JABEN (_U_(0x1) << PHY_ICS_JABEN_Pos)
145 
146 // PHY_LMD : Ethernet Phy Register 1Dh - LinkMD Control/Status
147 #define PHY_LMD_FC_Pos 0
148 #define PHY_LMD_FC_Msk (_U_(0x1FF) << PHY_LMD_FC_Pos)
149 #define PHY_LMD_FC(value) (PHY_LMD_FC_Msk & ((value) << PHY_LMD_FC_Pos))
150 #define PHY_LMD_SCI_Pos 12
151 #define PHY_LMD_SCI (_U_(0x1) << PHY_LMD_SCI_Pos)
152 #define PHY_LMD_CDTR_Pos 13
153 #define PHY_LMD_CDTR_Msk (_U_(0x3) << PHY_LMD_CDTR_Pos)
154 #define PHY_LMD_CDTR(value) (PHY_LMD_CDTR_Msk & ((value) << PHY_LMD_CDTR_Pos))
155 #define PHY_LMD_CDEN_Pos 15
156 #define PHY_LMD_CDEN (_U_(0x1) << PHY_LMD_CDEN_Pos)
157 
158 #endif // !HIDE_FROM_DOXYGEN
159 
160 #endif // !__PHY_H__
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